Numerous integrated circuits are typically fabricated simultaneously on a single semiconductor wafer. At certain stages of fabrication, it is often necessary to polish a surface of the semiconductor wafer. In general, a semiconductor wafer is polished to remove high topography, and surface defects such as crystal lattice damage, scratches, roughness, or embedded particles of dirt or dust. This polishing process is often referred to as chemical mechanical planarization (CMP) and is utilized to improve the quality and reliability of semiconductor devices.
The conventional CMP process utilizes endpoint detection techniques or predetermined fixed-time polishing techniques to determine when to stop polishing. Both of these polishing stop techniques produce non-uniformities across the polished surface due to polishing rate variations. In addition, over-polishing, meaning excessive thinning of a functional layer, causes the functional layer to become too thin to be operated on. Thus, an improved composition or method for CMP processing is still in great demand.